module ysyx_22040213_instram (
	  input rst,
	  input clk,
	  
	  // ram enable
	  input instram_req,
	  input wr,
	  input [2:0] size,
	  input [63:0] addr,
	  input [7:0] wstrb,
	  input [63:0] wdata,
	   
	  output reg addr_ok,
	  output reg data_ok,
	  output reg [63:0] instt
);
	/* verilator lint_off UNUSED */
	//add one clk delay//
	always @(posedge clk)begin
		if(rst)begin
		  instt <= o_ram_inst;
	          data_ok <= 1'b0;
		end
		if(instram_req && !wr)begin
		  instt <= o_ram_inst;
		  data_ok <= 1'b1;
	  	end else begin
		  data_ok <= 1'b0;
		end
	end

	// simulated a ram//
	import "DPI-C" function void mpmem_read(input longint raddr, output longint rdata);	
	import "DPI-C" function void mpmem_write(input longint waddr, input longint wdata, input byte wmask);
	reg [63:0] o_ram_inst;

	wire [63:0] w_data;
	assign w_data  = |size && |wstrb ? wdata : 64'b0 ; //no used

	always @(*) begin
		if(!rst)begin
      	  	  mpmem_read(addr, o_ram_inst);
		  addr_ok = 1'b0;
		end
		else if(!wr) begin //read model
      	  	  mpmem_read(addr, o_ram_inst);
		  addr_ok = 1'b1;
	        end
		else begin //write
		  mpmem_write(addr,w_data,wstrb);
		  o_ram_inst = 64'b0;
		  addr_ok = 1'b1;
		end
  	end
 endmodule
